SN5410J

Technical Characteristics

• Design Function And Quantity

  1 gate, nand

• Operating Temp Range

  -55.0/+125.0 deg celsius

• Test Data Document

  80063-sm-b-641498 drawing (this is the basic governing drawing, such as a contractor drawing, original equipment manufacturer drawing, etc.; excludes any specification, standard or other document that may be referenced in a basic governing drawing)

• Input Circuit Pattern

  4 input

• Body Width

  0.220 inches minimum and 0.280 inches maximum

• Time Rating Per Chacteristic

  29.00 nanoseconds maximum propagation delay time, low to high level output and 15.00 nanoseconds maximum propagation delay time, high to low level output

• Body Height

  0.140 inches minimum and 0.180 inches maximum

• Storage Temp Range

  -65.0/+150.0 deg celsius

• Case Outline Source And Designator

  to-116 joint electron device engineering council

• Features Provided

  monolithic and hermetically sealed and positive outputs

• Inclosure Material

  ceramic and glass

• Body Length

  0.660 inches minimum and 0.785 inches maximum

• Inclosure Configuration

  dual-in-line

• Output Logic Form

  transistor-transistor logic